This invention relates, in general, to integrated circuits and, more specifically, to output line configurations of very large scale CMOS integrated circuits.
It is advantageous to reduce the power consumption of integrated circuits both for power economy of the circuit into which the integrated circuit will be used, and for efficiency and material tolerances within the chip itself. CMOS integrated circuits are well known to exhibit very little power consumption compared to many conventional integrated circuits. Therefore, they are used in applications where power consumption is of critical importance. Because of this importance, it is beneficial and advantageous to provide CMOS integrated circuits which exhibit the least amount of power consumption possible.
In the present state of the art, the power consumption of the logic gates and transistors comprising the CMOS integrated circuit is very small. A large portion of the total power consumption of a CMOS integrated circuit is caused by state changes, that is, changes between 0 and 1 or 1 and 0, at the output lines of the integrated circuit. This is due mainly to the capacitance of the output lines impeding the change from one state to another. Therefore, the number of output lines of the integrated circuit which change state upon operation of the device significantly contributes to the total power consumption of the device.
Because of the ease of incorporating extra gates and transistors into an integrated circuit chip, power reducing techniques which require extra gates or transistors in an integrated circuit are not necessarily unattractive. Because of this fact, the trade-off between extra gates in the integrated circuit and the reduced power consumption afforded by their use may be justified. The use of additional output lines for the integrated circuit to accomplish reduced power consumption also follows the same rationale.
Therefore, it is desirable, and it is an object of this invention, to reduce the power consumption of a CMOS integrated circuit by using a unique configuration even though it requires additional output lines and logic gates and transistors within the integrated circuit.